Research On IP Core Technology Of Matrix Algorithm Based On FPGA

Nowadays matrix operations is widely used in signal processing system, and plays a role in many applications, such as scientific computation, digital signal processing and image processing. Therefore, it is significant to realize the the high performance of the matrix operations. With the continuous development of semiconductor technology, FPGAs have not only extremely rich operation and logic resources, but also other advantages like good flexibility, high energy consumption ratio and reconfigurability. So, studying the design technology about matrix algorithm based on FPGAs has great engineering application value.In order to achieve the effective transmission of data in matrix operations, this thesis studied the interconnection technology of SRIO, and adopted a mechanism about address mapping to support the dynamic access to the storage space on the bord, then designed and completed the IP core of high-speed SRIO communication interface. This thesis studied the method to realize the matrix transpose, analyzed the characteristics and applicability of different storage medium in-depth, proposed a transpose structure based on multistage cache, then designed and completed the matrix transpose IP core based on DDR+QDR, which can achieve the matrix transpose algorithm with higher data passing rate. This thesis analyzed the operation characteristics and data dependencies about covariance and generalized inner product, and designed and completed the covariance IP core, generalized inner product IP core and weights IP core, which have good scalability and can support for the parameters of dynamic configuration.Combined with an advanced verification methodology, this thesis completed the verification platform based on SystemVerilog, improved the efficiency of the debugging of the algorithm IP core. Finally this thesis set up the hardware experimental platform and verified the validity of the algorithm IP core designed in this thesis, which can reach to 18.68Gflops at 200 MHz clock frequency.