Implementation Of A Large-point Accelerate Unit In Heterogeneous Multi-Processor SoC

With the development of Multi-processor technology, IC industry enters theareas of mass data processing and intensive computing.FFT/IFFT is one of thetypical data-processing in this area and is an important part in modern signalprocess. It is very important to do research the key technology used in FFT/IFFThardware accelerate module which is often a key component of a high real timedata signal processing system.The main tasks of this paper are as below:1. Study the characteristics of classic FFT/IFFT algorithms, theircomputational complexity and hardware implement architecture, and select theappropriate algorithm and hardware scheme.2. Aimed at the process of FFT, establish the architecture for FFT processorwhich is suitable for the Heterogeneous Multi-Processor System-on-Chip andintroduce its computing unit, memory organization, control element, interfaces andsignals for the system.3. Complete the design and simulation for all modules design with RTL, usethe MATLAB operation results as baseline, do error analysis between baseline andFFT simulation results whereas points vary from32to16K, to prove the technicalfeasibility.4. The FFT/IFFT processor which is implemented on FPGA is verified bysoftware and hardware co-verification.