Research Of Hardware Acceleration Technique For Critical Algorithms Of DSP Applications

With the development of circuit integration, new situation and tendency of architecture design had appeared. In the real time processing systems which require high calculating performance, putting general purpose CPU and high-speed coprocessors together had becomed a new direction. Base on deep research on some typical applications such as Synthetic Aperture Radar (SAR), Software Radio (SR) etc, we pick up the key functions, such as ld_fft, 2d_fft, matrix multiplication, FIR filter, Digital Down Converter (DDC) etc as our research objects of hardware acceleration. Considering the different data transmission fashions, we present two kinds of system structure which is named interrupt data transmission system structure and DMA data transmission system structure.According to the feature of FFT butterfly algorithm, we design an optimized 32-bit ANSI/IEEE Std 754-1985 floating point operating component,and implement two parallel structures on FPGA, one is a parallel system consisting of a few ping-pong structural modules, the other is pipeline structure. Then we analyze the bandwidth it can meet and the hardware cost. According to some specific needs, we propose a common implementation structure of very long FFT algorithm.Considering the large quantity of data and high local storage requirements of 2d_fft, we propose three implementation structures which are called Hardware Implementation Structure, Hardware-Software Cooperation Implementation Structure and Software Scheduling Implementation Structure. Using the Hardware-Software Cooperation Implementation Structure, we implement a typical 2d_fft of (2048,2048) pointsMatrix operation, which is widely used in atomic simulation, calculating hydrodynamic, oceanic environment simulation and numerical weather forecast etc.is the most important numerical calculation.We propose a general matrix multiplication algorithm, which is applicable for arbitrary matrix sizes and arbitrary divisiory block sizes. Considering the limitations of local storage, I/O bandwidth, and the number of computational logic units, we introduce a scalable linear multiplication algorithm. Then, there is performance analysis.FIR filter is one of the most important methods in digital signal processing. The paper represent three structures of FIR filter implementation, and we draw a conclusion that FFT and floating-point multiplier can be used to implement fast coil structure of it. Digital Down Converter is a key feasible solution in current software radio and the paper make a certain analysis and research in the end.