Design And Hardware Implementation Of A 2-D High Speed Sliding FFT Processor

In the process of real-time signal processing,FFT is widely used because of its less computation than the accelerated discrete Fourier transform(DFT).However,with the development of the times,people have higher and higher requirements for real-time signal.Sometimes,FFT algorithm can not meet the engineering requirements.So some people have calculated the sliding FFT algorithm.Compared with FFT algorithm,it has higher real-time performance,so the sliding FFT processor has very strong practical significance and application value.This paper studies the FFT algorithm,FFT hardware implementation structure and the factors affecting the performance of the processor.Based on the above work,a 2-D sliding FFT processor is designed.The verification environment is built by Xilinx virtex72000 t FPGA,and the logic synthesis and back-end implementation are completed under TSMC 28 nm process.The simulation and verification results show that all the functions of the 2-D sliding FFT processor designed in this paper are correct and meet the design objectives.The main research work of this paper is as follows:1.Research and analyze the algorithm principle,algorithm complexity,computational complexity and hardware implementation difficulty of various FFT algorithms,analyze the advantages and disadvantages of four commonly used FFT processor architectures,and use a 2-D sliding FFT architecture to achieve 1-D sliding FFT operation according to the demand.2.The base-16 FFT core designed in this paper can switch different computing modes according to the configuration information,and the conflict free address rule of 2-D FFT result number storage is designed,which is suitable for the case that the output throughput is greater than the input.High base booth coding is used to optimize the Floating-Point Multiplier,optimize its logic structure,and improve the working frequency of the whole project.3.This paper completes the hardware test and verification of FFT processor on Xilinx virtex7 2000 t FPGA.The verification results show that the designed 2-D sliding FFT processor supports 32 bit single precision floating-point FFT operation,the length of sliding window is 64-256,the sliding step size is 4-16,the average error is 10-5,and the signal-to-noise ratio is above 120 d B.This paper also completed the logic synthesis and back-end implementation in TSMC 28 nm process.