The Synthesis Of High-Speed Very Narrow Pulse

As a kind of general test equipment, the pulse generator provides effectiveexcitation signal for the system test. With the rapid development of electronictechnology, it is universally accepted that the swifter the system is, the higher therequirement of test signal speed is. Moreover, in the applications of ultra widebandcommunication and integrated circuit testing system, the bandwidth of the pulse signalhas been pushed to a much higher level. In order to meet the requirements of the pulsesignal, it is necessary to carry out the research of very narrow pulse synthesistechnology.With the increase of the pulse’s repetition frequency and the decrease of the pulsewidth, the signal synthesis becomes more and more difficult. In order to study the highspeed very narrow pulse synthesis technology, firstly, the characteristics of rectangularpulse signal is analyzed in this paper. Based on the previous analysis, the rectangularpulse signal can be considered as a set of step signals. By simulating the high and lowlevel of the pulse signal with data ‘1’ or ‘0’ respectively, the high-speed pulse signal canbe synthesized. In this work, the FPGA is used as a control core, using a method of “lowspeed read, high speed parallel to serial” to generate a high-speed serial pulse signal.Under the control of output model and data editing of data, synthesizing monopoles andburst of pulses can be generated, and its highest frequency is up to1.5GHz. High-speedserial pulse signal is fed to the subsequent circuit, with the technique of truncating therelative time delay between the interception of the rising edge of the trigger signal andthe falling edge of the trigger signal, it is able to synthesis a very narrow pulse signalwith width of200ps.The main content and research results of this paper:1. Study on the characteristics of rectangle pulse signal waveform and its relevantparameters;2. Study on the structure and principle of the general pulse generator;3. By combined with the two methods: the high speed pulse sequence synthesisand very narrow pulse signal synthesis, a general system was proposed. 4. Completed the circuit design of each function module according to the generalplan;5. Completed the FPGA’s internal logic circuit design and the debugging ofhardware circuit, realized synthesis of the high speed very narrow pulse signal.