Design Of Link Layer Soft Core Based On IEEE-1394

With the continued integration of home appliances and computer technologies, therequirement of information transmission for multimedia is increasing higher and higher.For high-speed transmission, point-to-point transmission, low cost, easy to use andsome other advantages, the IEEE-1394high-performance serial bus is now widely usedin today’s high-speed transmission multimedia device.Based on the IEEE-1394protocol system, taking a top-down design methodology,the1394link layer functions should have a division of the functional modules. Thelink layer chip RTL-level design consists of link core, host interface, DM interface,CFR and FIFO modules. Link core module schedules data, calculats and checks CRCwhen link layer is sending or receiving packets. PHY/link interface is designed inaccordance with the1394protocol defined. Burst mode of host interface can be used togreatly improve the efficiency of reading and writting data. According to RTL-leveldesign, link layer chip functional simulation is done, which includes sending andreceiving acknowledge packet isochronous packet, cycle start package, three kinds ofasynchronous packet as well as receiving physical layer simulation package andself-identity package. Simulation results fully compliant with the IEEE-1394standard,and data and commands are transmitted properly, which prove the availability of theIEEE-1394link layer soft-core design in this article.