VLSI Design Of CCSDS Image Data Compression Algorithm

With the rapid development of remote sensing technology, the image resolution isbecoming higher and higher. Space missions are faced with the pressure of handling anextensive amount of imaging data with limited storage and bandwidth. Imagecompression technology is considered as the best solution to this problem. In2005,Consultative Committee for Space Data Systems established a Recommended Standardfor a data compression algorithm, namely CCSDS122.0-B-1(Image Data Compression)standard.CCSDS-IDC has low algorithm complexity and it supports fast and low powerhardware implementation. Therefore, it’s widely used in space missions.The Bit-Plane Encoder (BPE) is the key part of CCSDS-IDC that encodes thecoefficients of Discrete Wavelet Transform (DWT). In common sense, it is consideredas the bottleneck of throughput performance and hardware resource consumption. Anefficient VLSI architecture of BPE implemented with parallel and pipeline technologyis proposed in this paper. In this architecture, the whole bit planes of each DWTcoefficient could be encoded simultaneously and pipeline is utilized to reuse somefunctional parts of the bit plane coding. The proposed architecture has beenimplemented in Xilinx XC2V3000FPGA, its throughput is improved and its resourceconsumption is reduced compared with the published architectures.