The Memory Access Control Of H.264Encoding System Based On FPGA

As a main video compression standard, H.264has been widely used due to its higher compression ratio. FPGA has a high-speed parallel processing capability, rich logic resources, implement the H.264encoding on FPGA has a significant meaning. This paper proposed a FPGA storage design scheme for H.264encoder based on the detailed analysis of H.264video coding standard. The scheme consists of multi-port access controller(MPAC) and several module-aimed data adapters. According to the proposed scheme, the FPGA designs and implementations of MPAC, de-blocking filter adapter(DBA) and motion estimation adapter(MEA) are discussed in detail.MPAC is the kernel of whole storage control and it is responsible for the conversion from simultaneous I/O requests of multiple modules to serial I/O request on DDR. The controller has three main functions, namely resolving the access conflict, setting up the access path priority and implementing special data path. For conflict resolving, we apply request queue with priorities; with respect to setting up the path priorities, we combine inner initializing with outer updating; as to special data path, the written of special long data is achieved by controlling data mask of DDR according to specific requirement of access module.The DBA uses the architecture of the combination of ping-pong buffer registers and transmitting ram cache. This architecture can ensure the adapter to handle output filtering data correctly even if MPAC is busy.In the design of motion estimation adapter, we propose a reasonable set of storage address generating mechanism for the reference data based on its updating characteristics. According to the position of current encoding macro-block, the adapter can calculate the corresponding DDR address of reference data. In the mean time, it sends reference data to motion estimation module according the request of bit width.The synthesis and simulation results on the xc6vlx240t hardware platform show that, MPAC uses up to7235slice registers,6161LUTs, and its highest working frequency can reach to269MHz. De-blocking filter adapter uses up to5593slice registers,20599LUTs, and4Block RAM, and the highest working frequency of DBA can reach195MHz,and takes11clock cycles to complete a macro-block luminance data storage, in the conflict-free situations. Motion estimation adapter uses up472slice registers,506LUTs, and8Block RAM, and the highest working frequency of MEA can reach to275MHz and it takes72clock cycles to read one reference macro-block data.