The Design And Realization Of Multi-port Memory Controller

With the farther development of data processing technology, the demand for mass storage products and high performance is becoming even more urgent. Because Synchronous Dynamic Random Access Memory(SDRAM) has the advantages of mass storage, high speed,burst read /write and low cost, which is widely used in various fields. The control of SDRAM is relatively complicated, with the design of its controller interface circuit being the key. As a part of the Embedded System Development Platform project, this task focuses on the design and implementation of FPGA-based multi-port memory controller, providing a new approach for circuit designs which need mass storage.This thesis firstly introduces the rationale of SDRAM and the interface specifications of system applications. After that a design of multi-port memory controller is presented, with details from overall concept to logic implementation. According to the timing characteristics of SDRAM, the design makes use of a VHDL state machine, with focus on the implementation of techniques of multi-port memory controller. The access of this multi-port memory is illustrated with ISA interface and parallel communication port applications as examples. Corresponding interface circuits are designed to implement multi-port access.Finally,this thesis introduces the process of logic synthesis and simulation,then a software package is developed for testing.It also provides the result of simulating and testing.