High-Speed And Low-Power Physical Design For A GHz DDS SOC Chip

The physical design of digital IC is the physical implementation process of IC design, also known as the back-end design. It is an essential part of the entire system-on-chip design. It is not only related to the function of the entire design, but the circuit performance, area, and power are greatly affected, and therefore has a very important role. The main task of the physical design are placement and routing which is very dependent on EDA tools.This thesis is to achieve the physical implementation of the digital module of a14bit-1GHz Direct Digital Synthesizer by using a variety of EDA tools. Based on Cadence Encounter tool, placement and routing of the design of14bit-1GHz DDS are completed, the main processes include:design import, floorplanning, power planning, standard cell placement, clock tree synthesis, routing and power analysis. Based on Mentor Calibre tool, the physical verification of the design is finished which includes two parts:design rule check and layout versus schematic. Based on Synopsys PrimeTime tool, the final static timing analysis was executed to ensure the performance of the design.This thesis is based on SMIC0.18μm1P6M standard CMOS technology library, using4DDS core parallel-to-serial method to achieve a14bit1GHz DDS.The effective area of the digital module is1270μm×950μm and the clock frequency can reach1GHz. The total power consumption is488.7mW.