Research On AES Based Mixed Encryption Algorithm And Its Implementation On FPGA

Cryptography plays an important role in the information technology of modern world. AES is one of the cryptography algorithms being widely used today. It is safe, fast and easy to be implemented into hardwares. However, AES also has some disadvantages, one of which is the complexity of keeping and maintaining the cipher keys. To resolve this problem, a mixed encryption method has been suggested. After some research on the current development of Cryptology, I came up with a mixed encryption algorithm, which is an mixed encryption of AES and RSA. This new encryption algorithm resolved the problem of maintaining large amount of keys while keeping most of the advantages that AES has. Also, I implemented the mixed encryption algorithm into both FPGA and ASIC(front end). In this thesis, several aspects of my work are covered as the following:1. Research and comparison of AES and RSA encryption systems, as well as the research of the feasibility of the mixing of AES and RSA.2. Combine AES and RSA encryption systems. Do the RTL coding of the new encryption system in Verilog HDL using Top-Down method. Then synthesis the design using XST and download the design into FPGA, the model number of which is xc2vl000. Verify the functions of the implemented design, which turned out to be correct.3. Implement the design into ASIC, including synthesis using Design Compiler, static timing analyze using Primetime and formal verification using Formality. The technology library used in the design is from TSMC which is a 0.25um technology. After all the process, the implemented design can run at a frequency of 25MHz and the gate count is about 170K.