Implementation Of Network Adapter Supports Virtualization And Bandwidth Sharing On FPGA

With the rapid development of Ethernet technology,10-Gigabit Ethernet technology has become mature. In addition, due to the continues improving CPU performance and the wider and wider bandwidth of PCI Express, it is possible to deploy 10-Gigabit Ethernet on the server platform in the form of network adapter via PCI Express. On the other hand, the development of virtual technology and the expansion of cloud computing cause a growing number of tenants and increasing workload in the data center. Therefore, limitations in traditional data center network have been revealed, which are concentrated in scalability and rational allocation of resources. The scalability refers to the high costs and reduced network quality brought by scale expansion. And the allocation of resources refers to the best-effort sharing manner of bandwidth unlike the allocation of hardware resources such as the CPU and memory is rational, which will lead to jams and unfair bandwidth allocation. As a result, the allocation of network resources has become a critical and difficult issue.Although many related technology solutions have been proposed, they all have some limitations. So far none of them is perfect. To solve these problems, we propose a solution of controlling the egress bandwidth with rack switch together, which solves the problem of bandwidth sharing to a certain degree. Furthermore, we implement the hardware part of the network adapter in server of the data center network topology.The hardware part of network adapter is implemented on the FPGA, by Altera’s Strativ IV 530 chip. The main technologies used are as follows:hardware communicates with the CPU using the DMA technology through the PCI Express; the interface of Ethernet is 10-Gigabit Ethernet; the scheduling of virtual machine queues uses the deficit round-robin scheduling.The main results of the design are as follows:in a word, the design solves the bandwidth allocation and the scalability issues to a certain degree. It supports 16 virtual machines on a single server; the number of virtual machines in a tenant can be dynamically distributed and controlled by software. In detail, on the basis of support PCI Express 2.0, using high-performance DMA technology, especially the rate of DMA read memory has been significantly improved to meet the design requirements; the MAC layer in 10-Gigabit Ethernet interface has been designed and implemented; the deficit round-robin scheduling has been implemented on the FPGA. In the process of implementation, we first carry out functional simulation, then test on the board, finally realize and verify the design.