The Implementation And Analysis Of The AES Algorithm Based On FPGA

Advanced Encryption Standard (AES) is the new Federal Information ProcessingStandard (FIPS) announced by the U.S. National Institute of Standards andTechnology (NIST), which is based on Rijndael algorithm. AES is a128bit blockcipher algorithm which has a very excellent encryption and decryption performance,and is very easy to be implemented. Since then, AES has been a widely adoptedstandard, and replaced the former standard DES.The Advanced Encryption Standard can be easily realized by software or directlyimplemented by hardware. Field programmable gate array (FPGA) can provide afaster, more flexible, and more customizable way to implement AES. This paperdiscusses the study of AES realization using FPGA chip and VHDL language. Therealization is simulated using Altera Corporation’s QuartusII software. In order toassess the performance of different design and hardware consumption, bothencryption and decryption transform has realized with different schemes, and useAltera FPGA chip for hardware evaluation.This paper has presented three different AES encryption/decryption designschemes, also provided three corresponding key expansion schemes which used togenerate round keys for all all iterations round. The first structure is fully iterativestructure which reuses the same hardware structure in all encryption/decryptioniteration rounds. By considering the throughput to hardware consumption ration, thispaper proposed second structure, the hybrid structure. The hybrid structure is acombination of iterative structure and pipeline structure; this hybrid structure can bedivided into single-stage pipelined AES structure and four-stage pipelined AESstructure in detail. This paper also gave the AES design recommendations for differentapplications by analysis of the structures of the above three. These three structureshave synthesis and implemented on Altera’s FPGA. These three structures were testedand verified using the on-chip logic analyzer. Basic iterative AES structure’sencryption speed can reach to1.51Gbps, the single-stage pipeline AES structure’sencryption rate can up to2.51Gbps. The third structure is the extension of thesingle-pipelined structure, and extended to four pipelined AES structure, which’sencryption efficiency increased to5.03Gbps. At the end of this paper, comparisons ofthese three structures are given.