VLSI Design Of H.264/AVC Motion Compensation Arithmetic

H.264video coding standard was developed by the Joint Video Teamcomposed by International Telecommunication Union (ITU-T) Video CodingExperts Group VCEG and the International Organization for Standardization (ISO)Moving Picture Experts Group MPEG, which is a new generation of video codecstandards. Since the beginning of its release, various applications has been appliedin many fields of real-time video transmission, Internet streaming, and digital videobroadcasting due to the excellent compression efficiency and codec performance.H.264, as a new generation of video coding standard, compared with previousstandard as H.263and MPEG-4has been improved in several key structuresincluding luma quarter accuracy motion estimation and motion compensation,multiple reference frame motion compensation and much more efficient entropyencoder. In technology to improve the H.264contrast to previous video codingstandard, video quality, compression efficiency and network adaptation make greatprogress.However, the improvement of the H.264video codec standard requires largecomputational complexity and implementation cost. H.264decoder simply softwaredesign will bring a greater degree of difficulty. Along with the continuousdevelopment of the EDA tools and semiconductor manufacturing technology,therefore, hardware solutions based on the H.264video coding standard become ahot topic in academia and industry.In this paper, the inter prediction motion compensation VLSI structure, whichis the highest degree of computational complexity and the longest access to thememory,was researched and designed. Based on depth study of the H.264videocoding standard and decoder reference software solutions,H.264high-definitiondecoder motion compensation program easily implemented in hardware wasproposed. The H.264HD decoder applied the reference pixel storage andinterpolation pipeline structure, interpolation data path and control path separation,luma interpolation and chrome interpolation parallel computing structure, which isnot only to meet the motion compensation decoding function but to improve theperformance of integrated circuits, narrow area, lower power consumption.After simulation, synthesis and performance analysis was implement，themotion compensation circuit designed in this paper has the same simulation resultscompared with the JM10.1software reference model. RTL model was synthesizedand gate-level netlist was generated based on SMIC180nm CMOS standard cell library. The synthesis results demonstrate motion compensation decoder working inthe120MHz frequency. The worst single macroblock interpolation clock cycles is30. That shows the motion compensation unit designed in this paper were fully ableto achieve the function of real-time high definition video decoding.