Design And Implementation Of Motion Compensation Module In AVS Decoder

AVS (Advanced Video Audio Standard) is the national standards with China's independent intellectual property rights. Its video standard was promulgated as the national standard by Ministry of Information Industry on February 2006, and implemented on March 1,2006. The standard is applied for high-definition and high-quality digital TV broadcasting, digital storage media, and other related applications. The motion compensation technology of AVS decoding is the main method to remove temporal redundancy. The technology eliminates redundant information with temporal correlation between continuous images, and it plays an important role to lower the code rate of frame and improves video compression performance. Motion compensation module is an important sub-module of video decoder, in a sense, the module determines almost the performance of video decoder.This paper researched the AVS standards, and analysed the motion compensation decoding principle and related algorithms. The algorithms includes of the Choice of Reference Image, Derivation of Motion Vector and Interpolation Filtering. This unit predicts the Motion Vector under the inter prediction mode, and fetches the reference images from the off-chip SDRAM for interpolation according to the motion vector and reference image index. Based on the analysis of the correlation algorithm, it proposed a feasible and efficient hardware circuit structure. The hardware architecture is divided into three parts:the Motion Vector Prediction Module, Reference Image Fetch Module and Interpolation Module. The modules use pipeline to transfer datas with each other to speed up the processing speed.In this paper, top-down design method was used. Based on the correct function, it has competed the hardware design, include:coordinating with other related modules and determining possible input and output interfaces, analysing the logic function and performance indicators, writing the module specification documents, designing the hardware architecture of motion compensation module and each sub-module, using the Verilog hardware description language to complete RTL-level modeling of the motion compensation module, writing the top-level testbench simulation files, using simulation tool VCS (Verilog Compiled Simulator) of Synopsys Inc for functional simulation of the module. According to 0.13 technology library of Taiwan Semiconductor Manufacturing Corporation (TSMC), it used Synopsys's Design Compile for logic synthesis under the appropriate integrated strategies and optimization tools. Synthesis and verification results indicate that the design of Motion Compensation module have achieved the required goals of this topic.