Inter-frame Coding Research And Vlsi Design For H.264

H.264/AVC is the newest video coding standard of ITU-T VCEG (Video Coding Experts Group) and ISO/IEC MPEG (Moving Picture Experts Group). There are several advanced coding algorithms in H.264/AVC, such as variable block sizes motion estimation (VBSME), quarter-sample-accuracy fractional motion estimation and multiple reference frames motion estimation and so on, so it improves the quality of video and efficiency of the coding. But the computational complexity of H.264/AVC is very large because of the introduction of these new coding algorithms. During inter-frame coding, motion estimation consists of integral motion estimation (IME) and fractional motion estimation (FME), they all have huge computational complexity in H.264/AVC. And experimental results have shown that motion estimation can consume over 50% of the total encoding time of H.264/AVC codec. Many people researched many fast motion estimations, such as three-step search, four-step search, large and small prism search and so on, but the data streams which are generated by these coding algorithm are disorder and disadvantageous to very large scale integration (VLSI) design. In order to meet the requirement of real-time, we must develop highly parallel VLSI structure for motion estimation.In H.264/AVC, the inter-frame coding consists of integral motion estimation (IME), fractional motion estimation (FME) and motion compensation (MC). And, the integral motion estimation (IME) module is responsible for motion estimation of multiple reference frames and big search range. The integral motion estimation can be highly parallel VLSI computing structures for fast rest-time encoding. Based on the integral motion estimation, the fractional motion estimation (FME) module is responsible for the 1/2 fractional pixel motion estimation and 1/4 fractional pixel motion estimation of the 41 sub-macro blocks, and the selection of the splitting mode. Based on the motion estimation, the motion compensation (MC) module is responsible for the computation of pixel difference between the pixel of the current macro and the pixel of the best match macro which is specified by motion vectors.Therefore, in the paper, some efficient VLSI structures have been proposed to improve the coding efficiency of motion estimation, saved the data throughput and improved the efficiency of the hardware resources. Such as, in the part of integral motion estimation (IME), the VLSI structure of my design is a two-dimensional systolic array, it can improve the reuse of the pixel data, and reduce the pixel data throughput with the memories which are distributed on the whole chip; in the part of the fractional motion estimation (FME), the half-pixel motion estimation and quarter-pixel motion estimation were finished simultaneously in my design to avoid the storage of the half-pixel, and save the storage capacity, and at the same time, in order to improve the regularity of the data stream, make my design is more conducive to hardware design, and reused the IP of the 4x4 fractional motion estimation, I split all of the sub-macro blocks which were generated by the seven splitting modes, then, I finished the fractional motion estimation of the larger sub-macro blocks with the 4x4 fractional motion estimation; in the part of the motion compensation (MC), the pixel difference of the best match macro and the current macro was computed after the half-pixel interpolation and quarter-pixel interpolation, so the motion compensation (MC) had the same VLSI structure as the 4x4 fractional motion estimation. Last, this paper gave the VLSI verification of some modules.