Permanent Magnet Synchronous Motor Controller By SOPC Design On FPGA

SOPC (System On Programmable Chip) is on-chip logic programming system, that is a special system on a chip, It is characterized by having a crop, upgrades, expansions and so on. In the SOPC design, we use the bus way to manage and coordinate the various types of IP modules in the system.Firstly, from the control object:a permanent magnet synchronous motor, and analyzes its mathematical model, indicating the use of vector control theory and control strategies using id=0, modeling and simulation in Matlab/Simlink environment, the simulation results show control strategy is feasible. FPGA (Field Programmable Gate Array) is a programmable semiconductor chip, elaborate its internal structure and working methods, then introduce the development trend of the next generation of hardware programmable logic device, This paper take the Cyclone Ⅲ EP3C25Q240C8N by Altera company for SOPC design. Then elaborate SOPC design flow, involving a number of key technologies in SOPC design, such as bus architecture technology, IP core reuse and software co-design technology, and discusses the its core Nios II soft-core processor systems.Secondly, introduce the architecture planning by SOPC on FPGA, which is the core unit of permanent magnet synchronous motor controller, and elaborate the design approach of hardware-based module IP of the Avalon Bus, such as svpwm, Clark-Park, Cordic, PI regulator and detection circuit, then a good distribution of the various modules corresponding to the address, then the Nios II processor to manage the hardware IP modules to achieve control through software programming. Doing different system experiment, we will encounter adjust various parameters and change the hardware modules, using SOPC design approach, parameter adjustments can be directly on the PC side software Nios II IDE, and hardware changes only need to be adjusted in SOPC Builder, no need to recompile and adjust all the hardware framework, which can greatly reduce the development cycle. In the SOPC design, the use of bus way to manage various hardware IP core can be reduce connection burden between hardware module compared to the way of pure hardware design process, and reduce the complexity of clock management.Finally, introduce the peripheral circuit of controller, is the stator current sampling and optical encoder conditioning circuit, through experimental platform, from open-loop to closed loop, gradually verification, given the relevant experimental data and waveforms, complete SOPC controller design.