Degradation Of Polycrystalline Silicon TFT Inverters

Degradation of polycrystalline silicon (poly-Si) thin film transistor (TFT)-basedCMOS inverters under AC operation is studied. Firstly, the previous on-state drain currentmodel of poly-Si TFTs is extended into kink current region by combining a kink currentmodel in RPI model. Based on the complete current model, the voltage transfercharacteristics of both fresh and degraded inverters are well described. Then, a two-stagedegradation performance of inverter under AC operation is observed. By comparing thefitting parameters of n-and p-TFT, hot carrier of the n-TFT and negative bias temperatureinstability of the p-TFT are assumed to be the competing degradation mechanismscontrolling the observed two-stage degradation of the inverter. Then, the assumption isproved by temperature experiment. Based on such mechanisms, degradation of inverterunder various AC operation conditions are qualitatively predicted. It is found that undergiven frequency and amplitude of the input pulse voltage, inverter’s degradation can stillbe effectively suppressed by increasing the pulse falling time, and/or decreasing the lowvoltage duration.