Characterization Methodology At The Substrate Terminal For Polycrystalline Silicon Thin Film Transistors

As polysilicon thin film transistors (TFTs) have been widely used in liquid crystal display, it becomes more and more important to study polysilicon TFTs. However, up to the present, the evaluation approaches in polysilicon TFTs are mainly at the source and drain terminals. In this paper, as general approaches at substrate terminal in MOSFETs, the charge pumping (CP) and substrate current (Isub) are applied to polysilicon TFTs.At first, CP is firstly optimized by adjusting the gate pulse transition times to eliminate the geometric component of the CP current (Icp). Improved Elliot curves similar to those in MOSFETs are obtained for polysilicon TFTs. Then, according to the general CP model, the model for Elliot curves of polysilicon TFTs is proposed. Besides, based on the improved CP, typical trap state density (Dt) energy distribution within upper part of the band-gap and mean Dt value ( Dt ) are reliably extracted in different approaches. Furthermore, a modified Dt extraction approach, where the influence of the CP geometric component is inherently avoided, is first proposed. In addition, CP is employed to investigate the degradation of TFTs.On the other hand, Isub in polysilicon TFTs is first studied. When the substrate voltage (Vsub) is very small, Isub is found to be driven by the recombination process and therefore relevant to Dt. Furthermore, controlled by Vg, the recombination area can vary from the whole channel area to the local region near drain, source or substrate terminal. Based on the mechanism, the model for the Isub-Vg curve is built. Finally, the Isub-Vg curve is applied to sensitively locate the hot carrier damage region and detect the locally increased Dt in this area.