The Study Of AIS Link Layer SOC Chip Based On FPGA

Nowadays, the maritime transportation industry is playing an irreplaceable role in the entire transportation industry. In the background maritime transportion rapidly developing, it’s even more important that providing more stable communication and security services for ships. AIS (Automatic Identification System), serving in VHF frequency range, is used to transmit and receive dynamic and static navigation information. Based on the navigation information AIS provides the services such as collision avoidance, determining the course and speed of ship, positioning and other functions. So AIS can guarantee the safety of the ship.This subject is designing the link layer SOC of AIS terminal. The link layer SOC chip is used to unpack the HDLC data received, pack the HDLC data for transmiting, drive the GMSK and communicate the ARM with C-BUS. This subject is designed and simulated in ISE12.3software environment with verilog language. And the chip is tested on Xilinx’s Virtex-4development board.In this design HDLC communication protocol of the AIS is studied and analysed. The design is divided into three parts. The first part includes the C-BUS to exchange information with ARM. The second part includes the HDLC data package module and the transmitting buffer module. The HDLC package function includes generating FCS bits, adding bit stuffing, adding start and end flag and etc. The third part includes the HDLC data unpack module and the receiving buffer module. HDLC unpack function includes checking FCS bits, removing bit stuffing, testing start and end flag and etc. The logic for above parts are designed and simulated in ISE12.3.The AIS baseband data processing functions in this design is an important part of the AIS, This design is a part of the National Support Program "the development of the AIS/GNSS shipborne navigation equipment technology and system"(2012BAH36B02).