Study And Implementation Of HDLC Protocol And PC/104Bus Based On FPGA

At the beginning of the design of computer network, the main function of data linklayer is to achieve reliable data transmission in the less reliable physical links through anumber of data link layer protocol. Therefore, high level data link control protocol (HDLC)emerges as the times require, it can ensure reliable data transmission, and it is designatedas the international standard ISO3309. HDLC protocol is a bit-oriented data link controlprotocol, the subset of HDLC is used by X.25, ISDN and Frame Relay networks.Becauseof the long time development and optimization of HDLC protocol, HDLC is widely usedin embedded systems and computer networks and other fields, HDLC protocolspecification is a brief introduction in this article, HDLC protocol functions are alsoanalyzed. The specifications of HDLC protocol are introduced in this paper and thefunctions of HDLC protocol are also analyzed. A HDLC module which functions can becut is implemented by field programmable gate array (FPGA). The design of the HDLCmodule includes the standard functions which are required by HDLC protocol, Frameformat and timing are to meet HDLC protocol specification. Frame format and timingmeet the HDLC protocol specification strictly. In addition, the system can automaticallyinitialize; the master and slave、baud rate of data transmission can be configured by theoperation of the relevant registers. It also can enable all the function modules. Thedivision of the functional modules is: the module of interface with the ARM, send module,receive module, frame check module, transmission baud rate control module. Theinterface module, send module and receiver module are elaborated in this paper. The othermodules are introduced briefly. The design of HDLC module is tested. The results of testare compared with the standard of HDLC protocol to evaluate the performance of themodule and suggest the improvements and optimization methods to the design of HDLC.Usually, PC/104bus is an integral part in embedded control systems. Therefore, thedesign and implementation of the PC/104bus is also a key element in this paper. Theinternational standard PC/104bus (IEEE-P996.1) is analyzed in detail. PC/104bus isdesigned for IEEE-P996.1by FPGA. PC/104bus devices are divided into PC/104busmaster and slave. The commercial PC/104slave device can be easily obtained. So thePC/104bus controller is implemented in the design that is PC/104master. In our design,the master can communicate with slave devices normally. The main function modules of PC/104bus controller are: the module of interface with ARM, the writing module, thereading module and interrupt control module. Finally, PC/104bus controller tests arecarried out based on PCM-3680hardware. The results of test are compared with thestandard of IEEE-P996.1to evaluate the performance of the PC/104bus and suggest theimprovements and optimization methods to the design of bus based on FPGA.