FPGA Based Implementation Of Data Link Layer Protocol For AIS

Automatic Identification System (AIS) transmits its information to the surrounding ships regularly, which operates in the Very High Frequency (VHF) channel. At the same time, it receives the real-time information of surrounding ships to achieve the mutual recognition of each other. AIS plays an important role in collision avoidance, strengthening the management of sea transportation and ensuring the safety of navigation. Obtaining data and sending data in time are very important for effective communication and avoiding the communication conflict in AIS. This paper mainly investigates the FPGA implementation of the data link layer protocol of AIS, namely VHDL programming based on Quartus ii software of Altera. It realizes the function of AIS data packing and unpacking and SOTDMA protocol.Firstly, the research background and development of AIS as well as the application situation are presented in this paper. And then, development environment, workflow, protocol stack, and the AIS message type are also analyzed. Moreover, the realization of AIS data link layer protocol is discussed, mainly focusing on FPGA implementations of packing and unpacking function in data link layer and SOTDMA protocol. In order to obtain the data, a GPS module is designed for receiving GPS information and extracting related position information from the received information. After data acquisition, a data packing module is designed for data assembling according to the frame format of AIS. A data unpacking module is developed to check and unpack the received data. The module of SOTDMA protocol is developed to choose time slot. It includes the initial module, network insert module, continuous frame module, and so on. The above modules realize the basic function of AIS data link layer protocol and fulfil the whole process from obtaining data to sending data at specific time slots. In addition, the testbench is also designed for the simulation in Modelsim to verify various functional modules. The simulations results prove the validity of the design.