Design And Implementation Of A High-Performance Digital If Receiver

The high-performance digital IF system is a key component in the TD-LTE wireless test set, it mainly completes IF signal processing in transmit and receive link. To accomplish the correct IF signal acquisition and reproduction, system needs high performance ADC and DAC. It also needs high-performance FPGA to process IF data. What is more, The system requires high-performance PLL chip to provide a low-jitter clock for each part, the system also need a variety of high-speed serial interfaces between the system and baseband processing board to exchange data.This paper mainly discusses the design and implementation of the high-performance digital IF system, it involves the study of the IF transceiver topology、system key device selection、system design、 schematic and PCB design、welding and field debugging, covers a full range of hardware systems development flew consists of requirements analysis、system design、detailed design、circuit building、soldering and debugging. The main content of this paper is as follows:1. Introduction of this paper’s background、current status and significance.2. Analysis of the position and role of the digital IF system in the entire tester the topology of the transceiver the selection of the FPGA, the overall design of the system is given followed.3. Details of each part presenting in this order:FPGA peripheral circuit receiving link、transmit link、clock circuits and power supply circuit. 4. Discuss PCB design flows, especially illustrates the PCB stack configuration、the method of high-density PCB layout the strategy of high-speed signal wiring.5. Depiction of the debugging skills of the key modules in the system including the matters need attention of the power supply module、 mixed analog-digital system debugging methodology, ADC and PLL test.6. Summary and outlook through the entire paper.