Research And Implementation Of Fpga Based Clock Synchronization Control System

The data bandwidth in Packet Transport Network (PTN) between two nodes has been up to1Gbit/s, and the support to traditional TDM services is indispensable. With such high-speed data transfer rate, the precise clock synchronization control technology has become a bottleneck which restricts the development of basis transport network and related test equipments. The test equipments of PTN device rely on precise clock synchronization technology to support the implementation of input and output data analog for time-division multiplexing services. To realize such network test equipment, this thesis has made a detailed research of the clock synchronization control system for the equipments, then elaborated its implementation, which focused on the design and implementation of the data link layer interface controller, the interconnection bus of Soc and the clock synchronization controller, as well-as the analysis and optimization of the auto timekeeping of clock synchronization.First of all, based on the problem of closed loop waiting for the customary method of data processing in the Ethernet protocol, this paper brought up an optimization method for the Ethernet data link layer data receiving process as the guidelines of high-speed digital circuit design, which achieved higher traffic, lower latency and storage loss. With the Combination of the open source bus interconnect systems and the key modules of Ethernet interface controller, this thesis then proposed the design and analysis of Ethernet interface controller and Soc bus interconnect subsystem. Secondly, based on the analysis of IEEE1588synchronization model, the thesis designed the receiving and answering rules for the various types of packets in communication link, including the key functional modules of synchronization engine based on FPGA. Thirdly, the fuzzy control algorithm was applied to design the timekeeping controller. To compensate the lack of error handlings in the single rule superimposed algorithm for the fuzzy rules establishment, this paper also proposed an optimized algorithm. Based on the experimental results of the clock calibration, the simulation by Matlab verified the improvement of the error correction performance for the optimization algorithm, and determined the error accuracy of the algorithm in the100optimized. At last, with the combination of BIST and contrast test theory, this paper proposed the related test program to fulfill the board-level testing according to the function of achieve synchronous control system. The test results showed that the synchronous control system can meet the index requirements of clock synchronization accuracy and the data transmission correctness for Ethernet with full load.