Design And Verification Of FPGA-based DDR3SDRAM Controller

Memory is an important part of computer system，it is one of key equipment whichdetermines the performance of computer system. With the development of semiconductortechnology as well as the improvement of integrated circuits manufacturing technology，theproblem of “Memory Wall” is becoming worse，it is hard for the memory to meet the“high-speed, high bandwidth，high-capacity” requirements of processor for data access andstorage, which limits the performance of computer system. DDR3SDRAM，as a new generationof DDR memory，is widely used because of its high-capacity, high-speed and compatibility. Theresearch for the DDR3controller has already become the focus of the computer field. FPGA，asa logic device, has the characteristics of flexible construction，high integration density and shortproduct development cycle. The fast development of FPGA accelerates application for productdesign, prototype verification, etc.By analyzing current research and development of memory controller and studied thetechnical specifications and related information of DDR3，this article puts forward a DDR3controller design scheme based on Altera’s FPGA with fully grasp of the DDR3structure,technical specifications as well as working principles. The scheme divides DDR3controllerdesign into controller and PHY，and describes functions and implementation of its internalmodule particularly. The article is focused on the design and verification of DDR3controller，thefollowing is the main work and achievementsof the DDR3controller design..1. Researched Studied and analyzed structure and working principle of DRAM In-depth,discussed new features as well as low-power design techniques of DDR3and so on, made a fullgrasp of working principles and process of DDR3.2. Divide the internal structure of DDR3controller, which comprises controller and PHY.Verilog is used for functional design of the two parts. functional simulation is carried out for thetotal design of DDR3controller by using Modelsim-Altera.3. The A FPGA Platform is built for DDR3verification. Implementation process on theFPGA platform of DDR3controller is introduced, function test and self-test is also carried onDDR3controller.4. Analyzed the memory control strategy and put forward optimization methodwhich usememory access order scheduling to reduce memory access delay.