Research On MPSoc Testing Technology

By integrating multiple cores into Mul-processor System on Chip (MPSoC), it can not only achieve high-prallel and low-power processing, but also bring design challegne such as muli-core testing. It has strong need to verify the synchronization between cores and guarantee the functional correctness. In this thesis, we address this problem from software debugging acceleration, JTAG based multi-core testing and hardware/software co-verification. The major work is as follows.1. We designed a fast soft debugging prototype for MPSoC based on FPGA. In software debugging for MPSoC, it will have lots of test vector. The traditional debugging methods have the slow speed by simulation. So we designed a MPSoC prototype and downloaded it into PFGA. This prototype can not only support embedded software debugging, but also support on-line programming. Experimental results show that this prototype can reduce the software debugging time more than100times faster.2. We designed a JTAG based multi-core testing platform. Based on the prior research that has JTAG based testing interface in every single-core, we designed a new test controller and clock synchronizer. This controller can synchronize the testing order and controller the testing steps to choose when to choose which core under test. We perform simulation RTL to verify this testing scheme. The experimental results show that this scheme can reduce both test time and resource.3. We verify the functionality of MPSoC at both RTL and FPGA prototype. By developing the same testing vector, we perform verification at both RTL and FPGA prototype level, and comparing the results. Experimental results show both correctness and effectiveness.