Research On Key Technologies Of MPSoC Based On NoC

With the development of integrated circuit (IC) technology, transistor density on IC becomes higher and higher, and hundreds of cores would be integrated onto a single chip in the future. Networok-on-Chip (NoC) provides execellent structral regularity, scalability, low power consumption, and high-performance on-chip communications for Multiprocessor System-on-Chip (MPSoC). And It can efficiently resolve the network problem of MPSoC, and has become the mainstream interconnection solutions. But in the design flow of MPSoC NoC-based, there are many challenges such as mapping, programming, and fault tolerance.The design methodology of NoC-based MPSoC, which has different characteristics from those of single-core SoC, has become a research focus in recent years. Distinguished from single-core SoC, MPSoC provides excellent scalability, parallel computing potential, and a large number of computing resources. How to effectively organize, manage and utilize these resources to meet the requirements of target applications are the key issues. Focusing on the application parallelization and on-chip communication component design of the NoC-based MPSoC typical design process, key technologies have been studied on task mapping and scheduling, parallel programming model, MPSoC communication optimization, and fault-tolerant router design in this dissertation.As a key step in the application parallelization design, the task graphs will be used as an input to task mapping and scheduling. And aiming at the target computing platform, task mapping and scheduling explores more effective allocation solutions for computing resources and communication link under some constraints. In this phase, the task graph generation and the computation characteristics of target platform are commonly independent, and the inherent parallelism of the task graph is difficult to explore. To solve this problem, a task-clustered based mapping and scheduling method, with optimization objective flexible controlled, is presented. In this method, a clustering operation is introduced between the task mapping and scheduling and the task graph generation. It transforms the original task graph to a cluster graph with smaller global communication overhead according to the characteristics of the target platform, which effectively reduces the inter-cluster communication volume, achieving better optimization. In the clustering process, by adopting a controllable task duplication scheme and by setting different objectives for latency and energy, the details of clustering process can be adjusted. This enables an effective trade-off between latency and energy, benefiting the system-level design exploration.Serving as the SW/HW interface, the programming model plays a key role in the parallel program implementation and efficient utilization of MPSoC resources. To improve the efficiency of multi-core software design, support dynamic resource management and improve system fault-tolerant capability, the motivation for MPSoC programming model is refined by analyzing multi-core software design process and taking into consideration the support for dynamic task mapping and node-level fault-tolerant framework. And an MPSoC Message-Passing Interface (MMPI), which is MPI standard compatible, portable, and has small memory and execution footprints, is proposed. The proposed model employs layered protocol stack and clearly defines the hardware and software design space. It decouples the hardware and software design by providing an abstract interface and makes parallel programming independence of task mapping by introducing the mapping file based initialization method. Thus it realizes an optimal multi-core software design flow with supporting to dynamic task mapping. Additionally, the virtual topology technology, which is a converting mechanism from virtual nodes to physical nodes, is introduced to provide uniform node address for the application layer. This not only makes the software programming free of physical node address change but also provides excellent node-level fault-tolerance.As a key component in the communication process of NoC-based MPSoC, the network interface (NI) is a key component to separate computation and communication. And the way of NI HW/SW co-work is a bottleneck of communication performance. Aiming at the NI Hardware Abstraction Layer design and optimization, by analyzing the MMPI-based distributed multi-core communication process, efficient ways to reduce communication cost are concluded. These are reducing the one-to-many message sending latency and improving the concurrent receiving efficiency of multiple messages. A broadcast optimization strategy implemented at the HAL to cut down the cost of data copy is proposed, which decrease the one-to-many message sending latency efficiently. To deal with the bottleneck of concurrent receiving of multiple messages, a novel NI receiving strategy which combines a Lookup Table (LUT) mechanism and DMA mode is presented. It fully takes into consideration reducing interaction times and improving the efficiency of long message communication, thus achieving high data receiving efficiency. The experimental results show that the proposed broadcast optimization strategy can effectively reduce data sending latency and can improve performance by over 30% compared to a simple broadcast. The proposed data receiving strategy can improve the performance by 40% compared to the typical solution. On some specific target applications, better performance can be achieved by combining the two strategies.In the NoC design, the router which can meet performance requirements and has low overhead and high fault tolerance capabilities is one of the key. For supporting fault-tolerant, router design usually brings large hardware cost and low network performance. To solve this problem, a low granularity high-performance low-overhead 2D-Mesh NoC fault-tolerant routing solution is proposed. And a low-overhead single-cycle fault-tolerant router is designed according to this solution. By proposing a fault-model, this fault-tolerant approach refines the failure type determination and properly distinguishes node fault and link fault, thus effectively reducing the fault-tolerant granularity and improving network performance. Compared to generic Virtual Channel router, we depart a single switch into two small ones for each dimension and abandoning virtual-channel mechanism so as to enormously reduce the area-cost. By introducing a dimension-switch,data packets can transfer between dimensions and routing flexibility is also supported. Evaluation results show that the proposed fault-tolerant method can effectively improve network performance. It also shows that the designed router has many advantages, such as low area overhead, excellent fault tolerance, and low network latency.