The Research Of The MPSoC's Communication Interconnect Technology

Advances in VLSI design techniques have made large complex Systems on Chip (SoC) a reality. The complexity of these SoCs calls for review and revision of on-chip communication techniques, the traditional on-chip bus is not suitable for the Multi-Processer SoC (MPSoC), the new on-chip communication technology should be considered. Network on Chip (NoC) has been suggested as the communication resource to overcome the on-chip physical interconnect issues for the MPSoCs. A number of architectures have been proposed for NoCs which connect reusable IP blocks on a communication network. The dissertation introduces the necessity of the NoC, then focuses on the NoC's communication characters and the key design technology, such as topology architecture, transmission protocol, etc.As the integrated circuits technology continues scaling, the circuits'frequency and integration scale constantly grows, the parasitic parameters of interconnect have become a key factor in VLSI design. It increases the delay and power consumption and makes the crosstalk noise more seriously. At the same time, how to lower the cost and shorten the time to market has become a great challenge to VLSI designers. The interconnect optimization techniques will help speeding up timing convergence, decreasing power and area, increasing signal integrity and reliability. It has becomes one of the hot topics in physical design. The dissertation discusses several technologies of the on-chip interconnect, and a new low swing differential signaling circuit for the on-chip global interconnect is proposed, which can reduce the interconnect delay and power dissipation.For the connection of the IP blocks and the communication network, the network interface is necessary, which is proposed for global synchronization. The dissertation designed a simple network interface module to communicate the IP cores and the communication network.