Research On Power Analysis Attack Countermeasures Facing Block Cipher Reconfigurable Architecture

In recent years,power analysis attacks,such as differential power analysis(DPA),is an effective method to gather the key,which challenges the security of the crypto chips.Although the Coarse Grained Reconfigurable Architecture(CGRA)implementation of block cipher algorithms has both flexibility and high efficiency,it is as vulnerable to power analysis attack as other implementations.Therefore,a power analysis attack countermeasure designed for block cipher CGRA with low area and throughput overhead is needed to ensure the security of cipher chip.In this thesis,several corresponding power analysis attack countermeasures is proposed for block cipher CGRA,which have a good performance against differential power attack with low area and throughput overhead.First,an innovative method based on random execution is proposed in this paper.By scrambling input data sequences and randomizing input data's execution order,the correspondence between intermediate data and power trace is changed,which reduces the correlation effectively and enhances the ability against DPA attacks.Then,another power analysis attack based on register randomization is proposed.It dynamically changes the datapath and data storge register to prevent the establishment of the Hamming Distance(HD)model,which can improve the capability against DPA attack based on HD model.Meanwhile,redundant registers and interconnect resources in the block cipher CGRA is used to reduce area and throughput overhead.The block cipher CGRA was implemented based on the SAKURA-G FPGA evaluation board and the DPA attack based on the Hamming distance and Hamming weight model is used to verify the capability against DPA,the experimental results show that the DPA resistance capability of the DES and AES algorithm are both more than 2,000,000 power traces.Then,the block cipher CGRA improved by proposed countermeasures was implemented by TSMC 45 nm process,with the frequency of 500 MHz and the throughput rate of 4.5Gbps(AES).The results show that after applying all the countermeasures proposed in this paper,the area overhead is only 9.94% and the throughput rate is reduced by 3.4%.