Based On The DSP Two Cache Low Power Research And Implementation

DSP (digital signal processor), is based on digital signal processing large amounts of information device. Working principle is the received analog signals into digital signals, and then, digital signal processing (such as weaken, strengthen, delete), finally the digital signal interpretation back to an analog signal or the specific environment. DSP has been in transportation, aviation, and network. Medical and other fields have been widely used. Then as integrated circuits continue to leap forward, its processing speed is more and more quick, technology constantly improving the degree of integration, more and more, and relative to the microprocessor, memory read and write speed increase slowly, between the speed difference is bigger and bigger, so that the memory of clumsy, result in serious bottleneck problems, thereby restricting the system the enhancement of the overall performance of. In a microprocessor and memory is added between a small capacity but fast cache can effectively solve this problem. The main research work of this thesis is to design and implement a DSP chip level two cache. Through in-depth study of G1000system structure and the inner two level storage structure, studied the modern cache design technology and theory, completed the two level cache (Cache) design and implementation. Among them, the level of Cache using the Harvard architecture, the instruction and data separately, namely LIP and LID, LIP is a Cache GPU command, only the read operation, did not modify the permissions; LID as a data Cache, group two read/write access, organization structure for two set associative mapping structure, using pseudo LRU replacement strategy and the write back write strategy, this design method can effectively improve the cache hit rate, improve the speed of reading and writing; L2two cache, using Princeton structure, namely the instruction and data can be mixed deposited together, dynamic and effective allocation of storage space, can not increase in capacity for improving the hit rate, in order to ensure the consistency of data, using the snoop query request to maintain the LID, LIP and L2data consistency. This design uses a monitoring group prediction algorithm based on pseudo-LRU and Valid bit and timestamp-based reconfigurable algorithm to reduce the power consumption of the Cache.Finally the design optimization, system simulation, on the debug board, two stage Cache controller has completed its throughout the chip in the assumes function.The innovation of this article: Commonly used replacement algorithm for the design of Cache, a pseudo-LRU replacement algorithm:the algorithm is based on the least recently used algorithm (LRU) improved algorithm can effectively avoid the use of counters, only eight registers can achieve a record number of visits counter.Reference of the write buffer:LID read miss-allocation of space to write miss allocate space Cache, if the write-miss data directly written into the L2, L2has a slow data transfer speeds and processing requests more than a long cycle, which will seriously affect the processing speed of the CPU. Refers to the Write buffer, you can write miss first temporary, the task of writing miss independent, free CPU write miss processing, and thus can increase the processing speed of the CPU.Make full use of the Cache works-time limitations and space limitations, group prediction algorithm based on pseudo-LRU and Valid bit to improve the hit rate of the group predicted.To reduce power consumption.but without sacrificing performance purposes. Use timestamps to effectively monitor the Cache hit rate, in order to dynamically configure SRAM/Cache capacity. Done to reduce power consumption but also ensures that the effect of the hit rate.