Research And Application Of Ldpc Decoding Method

With the invention and successful of turbo code, Low Density Parity Check (LDPC) code was rediscovered. LDPC code can also achieve near capacity performance, and is already one focal point of research on error-control coding and one of the key enabling technologies of future wideband mobile communications systems. This paper mainly investigates the decoding algorithms of LDPC coded systems.Firstly, two kinds of decoding algorithm of LDPC codes are investigated for AWGN channel. The hard-decision decoding algorithms, which include Bit Filling (BF) algorithm. Weighted Bit Filling (WBF) and Modified Weighted Bit Filling (MWBF) algorithm, are presented first, Then we discuss the soft-decision decoding algorithm, Belief Propagation (BP) algorithm, Minimum Sum (MS) algorithm and its modified versions. Belief Propagation (BP) algorithm has a relative high complexity due to the multiplications in computing the soft information of check nodes. To reduce the complexity of BP decoding, MS algorithm is introduced. However, MS algorithm has a severely performance loss in comparison with BP algorithm. In order to improve the performance of MS algorithm, many modified MS algorithm have been studied. Simulation results show that performance of soft-decision algorithm achieves a huge performance gain than hard-decision algorithm, and modified MS algorithms achieve significant performance gain than the MS algorithm and the gap between modified MS algorithm and BP algorithm is small.Secondly, we investigate the performance of LDPC codes with high constellation modulation for AWGN channel. The high order modulation used is16QAM and64QAM with gray mapping. To simulation the LDPC decoding in the high order modulation scenario, two types of soft demodulation are introduced. The decoding algorithms used in this chapter are the same with those in Chapter III except the WBF and MWBF algorithm. Simulation results show that the BER performance of LDPC decoding in case of64QAM and16QAM is consistent with that of BPSK.Finally, hardware design of the MS decoding algorithm is presented. The float-point algorithm of MS decoding is converted to fix-point algorithm by means of simulation. Hardware implementation employs partial parallel architecture, and is mainly comprise of VFU and CFU module. To show the complexity of this design, we also give the FPGA implementation results.