Research And Hardware Implementation Of ADMM-LP Decoding Algorithm For LDPC Codes

In the research field of channel coding,Low Density Parity Check(LDPC)codes have attracted the attention of many researchers because of their excellent performance,infinite close to Shannon limit,and simple coding.In the research of LDPC codes decoding algorithm,Linear Programming(LP)decoding algorithm based on Alternating Direction Method of Multiplier(ADMM)has great research potential and attracts much attention.Compared with the traditional Belief Propagation(BP)decoding algorithm,the ADMM-LP decoding algorithm not only eliminates the influence of error floor but also has a Maximum Likelihood(ML)guarantee.The ADMM-LP decoding algorithm based on linear programming algorithm,combined with convex optimization theory,has a perfect mathematical theory reference,a benefit to modeling analysis.In the ADMM-LP decoding algorithm,the Euclidean projection of vectors on the check polytope is the most complex and time-consuming operation,and the projection complexity will increase sharply with the increase of the dimension of the vectors to be projected.Many researchers have proposed simplified projection algorithms,such as Cut Search Algorithm(CSA),Line Segment Projection Algorithm(LSA),etc.The key to the application of the ADMM-LP decoding algorithm in practice lies in the hardware implementation,so it is of great significance to carry out the hardware implementation research of the ADMM-LP decoding algorithm.With the continuous development of semiconductor devices,the computing power of hardware platforms is gradually rising,and the research of decoding algorithm hardware implementation based on Field Programmable Logic Gate Array(FPGA)has attracted more and more researchers'attention.The main work in this thesis is summarized as follows:1.This thesis optimizes the line segment projection algorithm.First,the LSA is simplified by removing the hypercube projection judgment and merging variables,and then a centered LSA is proposed.This thesis also carries out quantitative research on the proposed method and the corresponding hardware implementation framework is designed.The simulation results show that the performance of the proposed method is the same as that of the original LSA,but the calculation is simpler and the variables are more concise.Furthermore,the hardware implementation of the proposed LSA is deployed on the FPGA platform.Combined with the frame error rate performance and the utilization of hardware resources,the optimal quantization scheme is analyzed.Compared with the hardware implementation of CSA projection algorithm,the computation efficiency of the proposed LSA IP is improved by 65%,LUT resource consumption is reduced by 86%,FF resource consumption is reduced by 96%,and DSP resource consumption is not required.2.Based on the hardware-friendly advantage of the centered LSA,this thesis implements an ADMM-LP decoder based on LSA.Firstly,a centered ADMM-LP decoding algorithm is introduced,then the corresponding hardware implementation framework is designed,and the hardware design of each module is analyzed in detail.Finally,a complete decoder test platform is deployed on the FPGA platform.The experimental results show that the implementation of the ADMM-LSA decoder,compared with another decoder,frame error rate performance is similar,but its cost in hardware resources and have made a greatly improve computing speed,LUT resource usage was reduced by 40%,FF resources reduced by 67%,DSP resources reduced by 54%,and the decoding speed increased by 30%.