Research On LDPC Decoding Algorithm And Hardware Implementation

Low Density Parity-Check Codes were first discovered by Gallager in the early 1960s and recently have been discovered and generalized. The main principle of LDPC Codes is use the low-density check matrix to describe linear block codes. So the complexity of the coder/decoder can be reduced and the use of iterative decoding algorithm makes yards long to relax the restrictions. The decoding algorithm and its implementation of LDPC code are the focus of this thesis.In this thesis, several iterative message passing algorithms for LDPC codes are considered. In beginning, Gallager suggested two iterative decoding algorithms, the hard decision and the soft decision algorithms. The latter has a better performance but the complexity for hardware complication is too high. Later, the Belief Propagation algorithm can be considered both the compromise. The LDPC decoder algorithm for the study focused on how to achieve the performance and complexity have made the best point of balance, it can be said of the current LDPC decoder algorithm is in a constant development.This thesis describes the BF algorithm, WBF algorithm, BP algorithm, Min-Sum algorithm and Normalization Min-Sum algorithm. And analyze the realization of its complexity, error rate, the decoding performance and so on. Then we propose a new approximation to the check update function in the min-sum decoding algorithm. The new check update rule computes only the absolute minimum and applies a correction to outgoing messages if required. It can reduce the complexity of the hardware complication with a well decoding performance.Finally, the thesis discusses the hardware realization of the LDPC decoder. We first analyzed three main hardware implementation architectures of LDPC decoder, including full parallel architecture, partly parallel architecture and serial architecture. Then we take the full parallel architecture and use the normalization min-sum algorithm to complete the design of the LDPC decoder. To demonstrate this design, a FPGA implementation of 504 1/2 regular LDPC code is realized using Altera Stratix EP1S80 device. The design is described in the VHDL language description and the max clock frequency can reach 120MHz. By performing maximum 10 decoding iterations, the decoder can achieve a maximum bit throughput of 60Mbps.