Design And Implement Of Configuration System Of High Density FPGA

At present, FPGA is100%factory tested. Designers can avoid the risk ofproducing ASIC. FPGA can be repeatedly programmed and be used easily, whichreduce designer’s development time. So the range of application of FPGA isincreasingly wider, including: communication, industry control, medical device andsome divice of our military equipment. High density FPGA is the most importantdevelop and research project of our company.As we all know, FPGA can be programmed repeatedly, as long as the FPGAresource is enough, it can achieve any user specified function. In order to achieve userfunction by FPGA, you need to write configuration bitstream which is generated by theuser design to the FPGA, after loading bitstream; it is a chip with specific function.Readback operation can be carried out after the configuration, that is, the user cancompare the readback data with the data which is used to configurate the FPGA. Thiscan verify that whether the bitstream is correctly written to the FPGA. The user can alsodo DES encryption of the bitstream, so encrypted bitstream is loaded into the FPGA. Inthis way, it can prevent others from stealing bitstream maliciously; the stealed datawithout kesy is completely useless. The configuration system has a decryption circuit inthe FPGA, which can decrypt the encrypted bitstream, the user only need to ensure thesecurity of the key, which can guarantee the security of bitstream.The configuration system of high desity FPGA described in the paper is designedby our company itself, which also designed on the basis of the original succeccedconfiguration system circuit, the configuration system use five methods to completeconfiguration, can do readback operation, and also decrypt the bitstream which isencrypted by software. This thesis describes the configuration, readback and bitstreamdecryption of FPGA configuration system, the specific content of the study are asfollows:1. Configuration researching aspect includes: the high desity FPGA architecture,the five configuration modes, the pin of configuration， configuration column stractureand configuration process. When loading the bitstream to the FPGA, researching how configuration circuit works step by step, i.e. how to write the bitstream to the FPGAinternal from from the configuration port, then how to form a frame configuration data,and finally writes a frame data into the FPGA internal SRAM array. Configurationresearching aspect also includes: the meaning of each line of the bitstream, the registersof configuration circuit, the packet type of configuration data, the frame buffer and soon.2. Readback researching aspect includes: two readback modes of the high desityFPGA, how to read the data in SRAM array through the frame buffer to FDRO framedata output register, and finally read out of the configuration port. Readback researchingaspect also includes: the setting of PC software when do readback operation, and the useof readback files which are generated by software, as well as how to compare thereadback data with the configuration bitstream, how the frame buffer is working，andhow signal changes in frame buffer during readback operation.3DES encryption/decryption aspect includes: triple DES encryption anddecryption algorithms, decryption circuit in the FPGA use three key to do"decryption-encryption–decryption” process to decrypt bitstream. I design the specific decryptioncircuit, which includes: the Key programming circuit, iterative calculation circuit,SubKey generating circuit. I also simulate and verify the correlation circuits.