FPGA Verificaiton Of Missile-Borne Radar Signal Processing Arithmetic Based On SoC

Traditional implementation of radar signal processing based on FPGA and DSPcan’t conform to the developing trend of electronic products to smaller size, less weightand lower power. So it is necessary to adopt the method of integrated system toimplement radar signal processing. But the flexibility of ASIC is insufficient whichlimits the area of application. Using System on Chip to complete the radar signalprocessing brings several advantages. On the one hand, the real-time performance andreliability of radar system are improved. On the others hand, the system volume isreduced. What’s more, the costs are lowered as well. At the same time, amicroprocessor is included, which makes the chip meet the requirements of universalproperty and multi-mode.The main contents of this paper consist of analyzing the procedure of radar signalprocessing and implementing SoC prototype design with FPGA. First, theimplementation structure of missile-borne radar system is chosen according to basicprinciple of radar signal processing. Then each radar signal processing module isanalyzed in detail, including Pulse Compression, MTD and CFAR, and the realizationof multi-mode configuration. The logic design and simulation of the radar signalprocessor is implemented in advanced FPGA, and the processing results are comparedwith Matlab，then the performance of the whole program is evaluated in this paper.Moreover, according to the system requirements, the reconfigurable circuit is alsodesigned. Last, the generation mechanism of radiation action and the methods ofanti-radiation, especially SEU, are presented in this paper. And the key parts of thecircuit are simulated through error injecting.