Radar Signal Processing System Design And Implementation Of Common Chip Verification

The general radar signal processing chip embedded a DSP processor is a SOCwhich is specially used for radar baseband signal processing. Because of the verilogcode of the chip has been realized, the verification system which can verify the code isurgent needed.To ensure the correctness of functions of the general radar signal processing chip, averification system based on FPGA and DSP is designed in this dissertation. Firstly, theprinciples and the algorithms of the radar signal processing have been analysed andsimulated. Secondly, the verilog code for ASIC which have the functions of the chip istransferred to the code for FPGA. Thirdly, the design of the verification system isdescribed in detail. At the end of this dissertation, test results of the the verificationsystem is introduced.The main content and work in this dissertation include:1. In the base of deeply understanding the principles of radar signal processing,of which the algorithms have been simulated by Matlab, including echo, pulsecompression, moving target indication, moving target detecting and CFAR.2. The verilog code for ASIC has been converted to its FPGA counterpart whichhas been simulated under VCS.3. According to the number of logical resource comsumption and the interface ofthe general radar signal processing chip, a solution of the radar signalprocessing system verification has been proposed, and the the schematic sheethas been completed.4. According to the timing requirements of I/O ports of the chip, the verilog codefor the signal generation and that for driver have been programmed.5. Debugging of the circuit units and verificating of the radar signal processingchip have been completed.