Based Multi-chip Dsp Radar Signal Parameter Estimation And Identification Hardware

The electronic reconnaissance usually use wideband receiver to implement signal recognition, parameter estimation and sorting of radar signal.The signal processing system not only have to meet the requirement of high sampling rate but also have to possess parallel processing capability to ensure real-time performance. In this dissertation, the time domain and frequency domain characteristcs of the monopulse signal, the linear frequency modulation signal (LFM) and the binary phase coded signal are analyzed firstly. Then the algorithms of recognition and parameter estimation for the three signals are studied and verified. Finally the scheme of high performance parallel DSP and large capacity FPGA is used, which are ADSP TS201S and Virtex-5 series FPGA. Radar signal processing platforms of single DSP and multiple DSPs are separately implemented by the external bus and linkport mixed coupling.The main contents of the thesis are presented as follows:1. Based on signal environment of modern radar countermeasure, models of the monopulse signal, the linear frequency modulation signal and the binary phase coded signal are introduced. The properties of time domain and frequency domain for these signals are studied.2. The fast algorithm for identifying the three signal modulation types is studied by comparing the bandwidth of the original signal with the bandwidth of the squared signal. The smoothing technology is used to improve the performance of the fast algorithm.The fast algorithm for parameter estimation is introduced.3. An algorithm based on characteristc parameter for radar signal identification is studied, which extracts two characteristic parameters mapping the bandwidth and frequency of radar signal based on the aperiodic autocorrelation function. The fast identification of four modulation types of radar signal is implemented according to the two characteristic parameters.4. High speed signal processing board of single DSP is completed based on ADSP TS201S and XC5VLX30, including schematic diagram design and PCB layout design. The high speed linkport transmission and bus transmission between DSP and FPGA is implemented. And the debugging of FPGA peripheral interface and algorithm software is completed. In addition, a display interface of radar signal parameter is written by LabVIEW.5. High speed signal processing board of two parallel DSP is completed based on ADSP TS201S and XC5VSX50T, including schematic diagram design and PCB layout design. The scheme of mixed coupling parallel DSPs is used and the particular RocketIO interface of Virtex-5 series FPGA is studied.6. To demonstrate the feasibility of radar signal processing algorithms, and practicability of hardware system, a hardware and software combine-test system is designed and testified.