SD Card Interface Circuit Design Based On Digital TV Chip

With the popularization of digital TV and the extended operation, the intelligenti-zed HDTV is becoming more prevalent. Digital high definition operation developsrapidly toward network. Recording, playing and auto controlling of HD programmemake a more highly requirement of HDTV and set-up box memorizer. SD card is onekind of removable memorizer which supports hot-plugging. Because of its suitablecapability of memory and removability, SD card is widely used in the field of thedigital products. This paper focus on the application of SD card using for HDTV andset-up box. The design of SD card host is compatible with SD physical layerspecification version3.0. SD host chooses SD bus mode communication. A single SDbus should connect a single SD card. SD card host copies data from GBUS(DDR2/DDR3memory) to SD card or copies data from SD card to GBUS. Thetransfer data length unit is512Byte. SD card host receives CPU command from CBUSand sends command to SD card accord SD bus specification. SD card host will storesome command responds in internal register and CPU can get these respond fromCBUS.The main structure of SD card interface circuit hardware contains registerconfigurable module, GBUS arbiter, buffer cells and SD card interface timingcontroller. Register configurable module CFG is the control center of the whole circuitusing for CPU config the internal register. GBUS arbiter operate data transfer betweenGBUS and buffer cell. Buffer cell store commands, responds and data. SD cardinterface timing controller decodes commands and specifies timing constraints of SDcard interface. The process of design verification includes logical function emulationand FPGA verification. SD behavior module and verification vectors are used forlogical function emulation. Verification vectors are set as drivers of the testbench usingfor the emulation of SD system commands and operation modes. FPGA verificationincludes C module set as software driver program and single command step used forverificate SD host instantiated in the FPGA environment. Bottom-up is adopted for SDhost synthesis. Analyse and calculate timing reports generated by top-down synthesiswith scripts. Specify strict input delay and output delay as the primary IO constraints.Set up violations can be reduced by this way. This paper advanced synthesis methodabout library format. Scripts run auto-generation of sub module’s library filesaccording to the format as foundry supplied. Find the interface information includingname, type, bit width, transiton and load value from the sub modules’ ddc timing reports. Run bottom-up synthesis with lib files of sub module. Lib files bottom-upsynthesis run faster compared with ddc bottom-up synthesis. This method reduces thesysthesis cycle.