Mixed Hardware/Software Accelerator-Centric Heterogeneous Architectures

Embedded systems have become an indispensable part of our daily lives.Smart phones,high-definition TVs,washing machines,and traction control systems in cars not only make us comfortable but also keep us safe.These systems require low cost,high performance,and energy efficiency that makes their design intricate and nontrivial.In order to achieve these requirements,accelerator-centric heterogeneous computing has emerged as the best way to utilize hardware more efficiently.This thesis investigates two approaches in the design of energy-efficient and high-performance embedded systems.The first approach involves tailoring the processor architecture based on application profiling.The second approach deals with the design and integration of application-specific accelerators into the processor datapath for performance enhancement.The first approach deals with the implementation of an instruction decompressor and the analysis of compression and decompression schemes used in the FlexCore processor.The instruction decompressor is designed and implemented in VHDL and is synthesized using the Cadence RTL compiler.The impact of different parameters on the compression scheme used for the implementation of the instruction decompressor in hardware is studied.The instruction decompressor greatly improves the performance of FlexCore since it saves the memory footprint.Later,basic arithmetic logic units(ALU)are implemented using two types of adder circuits,a ripple carry adder(RCA)and a Sklansky(SKL)adder.The ALU is designed using an application specific integrated circuit(ASIC)platform,where VHDL and standard cells are used.The synthesis results show that the area of ALU-RCA changes more rapidly than ALU-SKL as the ALU-RCA has to put more effort to meet the stricter timing constraint.The ALU-SKL which has a fast adder easily meets the stricter timing constraint without increasing the area and power consumption.It is also observed that the ALU-RCA uses less area and power as compared to ALU-SKL if the timing constraint is not high.In the second approach,the design and implementation of specialized hardware accelerator blocks for Coordinate Rotation Digital Computer(CORDIC),Cyclic Redundancy Check(CRC)and Viterbi algorithms are presented.The hardware accelerators are integrated with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency.These algorithms are selected because they are widely used in signal processing and communication systems.The mixed hardware/software implementation of these algorithms results in achieving higher performance and area/energy efficiency.The accelerated embedded processor datapath achieved a 14 times,a 153 times,and a 4 times increase in performance and energy efficiency for the CORDIC,the CRC,and the Viterbi algorithms,respectively.The CORDIC accelerator is area efficient as it saved four multipliers and two adders.Finally,two design examples of application specific heterogeneous architectures are presented.The first design deals with the implementation of the Field Programmable Gate Array(FPGA)prototype digital hearing aid.The project is divided into three different phases:software only,mixed hardware/software and complete hardware implementation.The second example deals with the implementation of a distance and speed measurement system.The FPGA project proceeded in three phases:All-in-C design using Microblaze processor,an accelerated design with custom co-processor,and full custom hardware design.Later,the complete system was implemented on an ASIC platform.The ASIC implementation optimized the modules for area and timing based on 130nm process technology.The strengths and weaknesses of the platforms used in the implementation of these systems and the impact of various attributes on performance are shown in this thesis.For example from the software phase to complete hardware implementation,the improvement is a 400x increase in performance and energy efficiency.Mixed hardware/software accelerator-centric heterogeneous architectures deliver order-of-magnitude higher performance and energy efficiency compared to the general-purpose hardware solutions.