Design And Verification On Computing And Decoding Units Of Automotive Microcontroller

Automotive electronics develops rapidly in modern automotive industry, inwhich ECU(Electrical Control Unit) plays an important role. The automotive needsmore ECUs to be integrated to suit for the requirement of intelligence and networking.However, the kernel component of the ECU is the microcontroller, most types ofwhich are produced by foreign manufacturers，it’s an obstacle for the development ofautomotive industry in our country. So it is neccery for carrying on the research anddevelopment of an automotive microcontroller which we have the intellectualproperty rights.Based on the analysis of characteristics of automotive microcontroller, theobjective of research is to design a Freescale CPU12instruction set compatible16-bitautomotive microcontroller. The core of microcontroller uses the mechanism of singleclock synchronized design and microcode control with the stability and flexibility.The main work of this thesis is the design and verification of the computing anddecoding units of the microcontroller. First, we propose the structure of computingunit which has a16-bit unified data path and fast computing modules. The proposeddata path can execute signed and unsigned operations of8-bit and16-bit of one kindof instructions using one computing module which avoids the repetition of computingmodule and decreases the area of computing unit. The result of evaluation shows thatthe computing unit can meet the requirement of microcontroller. Second，based on theanalysis of construction and characteristics of all instructions, a decoding scheme ofCPU12instruction set is proposed. It can accelerate the reading of instruction bytesand the generation of decoding information combined with the prefetching mechanismwhich promotes the efficiency of microcontroller.Confronted with the verification challenge that complex design brings, relatedresearches are done about verification language and methodology. A reusableverification platform is built based on UVM（Universal Verification Methodology）toaccomplish the module level verification based on coverage and assertion which canpromote the quality of the design and verification. The paper designs a randomconstrained transaction level instruction generator which can generate a variety ofrequired instructions effectively and decrease the manual directed stimulus greatly.Incorporated with concurrent assertion designed for interface signals and internal states, the process of module level debugging and verification closure are acceleratedto accomplish the relatively comprehensive verification of the modules. System leveldebugging and FPGA prototype test is done at last.