DSP Kernel IP Verification Via FPGA Incremental Compilation

The emergence of FPGA prototype verification has greatly improved the efficiencyof chip verification.FPGA prototype verification makes designers test a large number ofprocedures in a short time and find the errors in the design earlier.At the sametime,massive chip verification makes compiling time longer.If there is a smallchange,the whole design has to be recompiled,which will waste much time and reducethe verification efficiency.During the verification process of the kernel IP of XXX DSP,we use theincremental design and split the design into partitons according to different functions ortiming critical paths.When we make a small change in the design,compiler will onlyrecompile the partitions which have been changed and the other partitions will remainthe last compiling result according to the netlist types specified by us.This processgreatly reduces the compiling time and improves the verification efficiency ofFPGA.The specific work in this paper covers the following aspects:Firstly,by the study of incremental compilation theory and design methods,we drawup the scheme of exporting and using IP core by Quartus II software.Secondly,we complete FPGA-to-ASIC conversion in RTL code.Then,through thefunction verification,we verify the correctness of the code conversion at the behaviorallevel.Thirdly,after exporting the kernel IP of DSP sucessfully,we use the incrementaldesign to built a IP verification environment which is based on Local MemoryBus(LMB),including a clock module,an IP module and an external instruction memorymodule.The external instruction memory module includes slave interface logic andmemory logic.In addition to split transmission,the slave interface logic supports for alltransmission types of LMB,such as a byte transfer,half-word transfer,wordtransfer,double-word transfer,read-modify-write transfer and variable length64bitsblock transfers.Actually memory logic is only a ROM,width64bits,depth2048,completed by synthetical RTL code.Finally,we verify the function of the kernel IP of DSP on the hardwareplatform.During this process,we give full play to the advantages of incrementalcompilation and improve the verification efficiency of FPGA.