Research And Design On Key Technologies Of High-speed Serial Data Transmission

The transmission loss in high-frequency is becoming the key factors which limitthe data rate and bit-error rate. Study of transmission medium and interface circuit is thepremise of realizing Equalization technology. To reduce the inter-symbol interference,the equalizer compensates the channel loss by boosting the higher frequencycomponents of signal, and thereby minimizes the amplitude difference between the lowand high frequency components of the bit stream. Therefore, a well-designed equalizercan effectively solve the data rate and bit-error rate and other issues.In this paper, high-speed serial data transmission system has been studiedextensively. First, starting from the interconnect model, we analyze the reasons for thechannel loss, and then establish the simulation model with channel characteristics.Second, this paper designs and optimizes a CML transceiver with SIMC0.13μm CMOSmixed-signal circuit technology based on high-speed, low noise, low power and lowcost CML circuit structure. On this basis, the transmitter combines the CML driverpre-emphasis circuit while receiver with nested CTLE equalizer. After careful designand optimizing in the case of1.2V core voltage and2.5V I/O voltage, Simulation showsthat transmission rate is up to10Gbps, compensating-30dB for channel loss withSpectre. In addition, based on the method of semi-custom standard cell-based ASICdesign, this paper designs a LMS algorithm FIR for adaptive equalizer with a4-orderFIR taps,16-bit data width and11-bit decimal precision in Verilog HDL. And this paperbuilds a unique Modelsim and Simulink co-simulation platform, which greatlysimplifies the algorithms and logic simulation step, making the verification processmore simple and concise.