Optimized Design Of Routing Algorithms In Network On Chip

With the rapid development of semiconductor technology, the performance of Systemson-Chip(SoC)was limited by the communication in cores. Quoting ideas of the distributed computing network communication mode, Network-on-Chip(NoC)technology employs routing and packet-switching to instead of traditional bus to realize data communication, which can improve the transmission performance significantly. It is a new design approach in very large scale integrated circuits.As the key in NoC designing, the routing algorithms become the main term. On the basis of analyzing in communication architecture of NoC, the paper aims at studying deeply in general routing algorithms and fault-tolerant routing mechanisms. The main work and contribution are depicted as follows:(1)According to the issues that the deterministic routing algorithm of on-chip network performance degradation is fast under the condition of high load and the adaptive routing algorithm has a high logical complexity and large cost, a routing algorithm called DARA is presented in this paper, which is applicable to the 2D-Mesh topology. On the basis of the shortest path to satisfy delay constraint, DARA adopts the dynamic routing to the center nodes which are easy to become hotspots, and uses deterministic routing to the edge based on the Turn Model. OPNET platform is used to execute a layered-modeling of NoC based on 2D-Mesh topology, Compared with the XY routing algorithm and DyXY routing algorithm, the result shows that the algorithm has a better performance in the hot spot pattern.(2)In reconfigurable routing based on single fault model,traditional routing algorithms are prone to load imbalance. In this dissertation, a fault-tolerant method is presented. On the basis of Built in Self Test, auxiliary nodes are set by the improved algorithm according to fault node in the network. By this method, the link can be balanced. OPNET platform is used to validate this strategy under different network sizes and positions of fault nodes. Compared with the original algorithm, the proposed algorithm has lower delay and higher throughput.