The FPGA Implementation Of Network-Turbo Coding

Relay is a hot research topic with more and more attention paid by industry fields in the Long Term Evolution-Advanced. The relay and cooperative techniques have attracted extensive attentions in the wireless communications due to the extra space diversity gain. The application of the network coding in relay networks can effectively improve the transmission rate and the throughput without the loss of diversity gain. This is one of the hot research in recent years.A new transmission scheme combined with turbo network coding is proposed in the thesis, which is based on multi-access relaying system model。In the model, the relay node decodes all the messages received from the multi-users firstly, then encodes the decoded messages together and forward the coded bits to the destination node. The destination node decodes the original messages with the received signals, which are from the source nodes and the relay node. We call the procedure network turbo code.After the hardware implementations, we analyzed the decoding principle of turbo codes, in addition, the thesis also studied the existing decoding algorithms, such as MAP, Log-MAP and Max-Log-MAP, the performances of these algorithms are also simulated and compared. Then, In order to improve the decoding speed, the improvements of algorithms and configurations are discussed in detail in condition of decoding performance, the hardware implementation complexity and resource consumption. In the aspect of the algorithm improvements, we simplified the Log-MAP decoding algorithm, which considerably reduced the complexity of the Log-MAP algorithm. In the aspect of the structure improvements, we adopt the parallel sliding method, which overcome the problem of decoding after receiving an entire frame data. The quantization of converting the floating-point to the fixed-point number is analyzed and verified by computer simulation.Finally, we give the FPGA implementation for each module.