Rfid Read/write Digital Baseband Receiver Down Sampling Filter Design

In recent years, with the increasing application of radio frequency identification technology in life, the requirements for the RFID system become more and more strict. In areas such as logistics management, most of the RFID system use passive tags because of its small volume, small area and its low power consumption. In addition to its many merits, the system requires higher performance of the reader. So there has a important application prospect to design a lower cost, higher integration and low cost single-chip UHF RFID reader.How to design a low power and high performance receiver is the important and difficult part. And the decimal filter group is the key module of the RFID receiver baseband, through decimating and filtering, it slows down the signal rate to meet the requirements of the following module. So their performance determines the effect of the receiver. This paper focus on the design of the module which consumption much resources. And based on the previous version, Extension the single data rate to complex data rate that meeting the requirements of the protocol. The design aims at reducing the area and resource consumption of the module.Though analyses the requirement of the EPC Class-1Generation-2protocol, research the radio resource allocation, and study the performance of the receiver, this work determines the design index of the decimal filter group first, and select the best architecture through the comparison of different methods. This dissertation introduces basic theories and architectures of the CIC filter and finds out the way the solution method of the gain and the finite word length increase effect, at the same time, this dissertation proposes new architectures of the HB filter and FIR filter to reduce the power consumption and save the hardware resources.The paper firstly introducing the principals of the decimal filter group, and then analysis the architecture of the module. After establish the module model in Matlab Simulink, the work complete the RTL verilog language description, and the use Modesim in circuit simulation and validation. Finally using the ISE tool achieve the module and the complete receiver. The comparison of result propose the design is effective and feasible.