Nfc Receiver And Design

NFC (Near Field Communication) is an expanded protocol based on tradional HF RFID protocol(ISO 14443A),to provide a security, convenient and swift short range wireless communication port as well as compatible with already existed HF RFID system,which is expected to have a bright future in applications such as personal financial aids. This paper focus on the research and design of the receiver in a single chip solution to NFC device.NFC protocol define two work mode:active and passive,with different data rate. Passive mode is defined to be compatible with already existed HF RFID system. NFC device may take part in the communication as RWD or transponder. Active mode is the unique point of NFC.Two NFC device have equal status,and communication with one another through TDMA HDX.In such mode,NFC device uses its own PA to generate magnetic field to communication. Unlike tradition HF transponder,which suffers a lot from strict power consumption limits,NFC can realize better compromise between read range, security and costs,thanks to the loose relativity between read range and power consumption.According to NFC protocol,NFC receiver have 3 work mode,in which the most challenged one is the RWD type in passive work mode. Actually,NFC receiver is quite like one in traditional 14443A RWD.The main difference is the NFC may require lower power consumption as a personal hand-held device. According to different requirement,different envelop detector and coherent demodulator have been designed. Coherent demodulator is based on sampling theory,and clock/power block is also design to the demodulator's needs.Sampling circuit made up of multi-stage switch move the ASK signal on a 13.56MHz carrier to zero IF,before amplifiers and filters are used.By proper filter design,offset of OP and strong carrier leakage cause no serious consequence. RC is used to realize the filter due to power consumption consideration. Full differential structure is used,and mismatch problem is taken into careful consideration during layout design. All critical signal route is shielded. Hysteresis comparator is ued instead of a more complicated AGC(Auto Gain Control) based on ADC(analog-digitalconverter) to reduce power consumption.Circuits have been taped out in SMIC 0.18 um EE process. Test work have been done.Test results and simulation results have no obvious difference,and design goal is realized.