Single-chip UHF RFID Reader Digital System And Its Implementation

Ultra-high frequency (UHF) radio-frequency identification (RFID) system has been widely used in recent years due to its long work range, fast inventory speed and large information capacity. Requirement of higher integration, lower cost and easier configuration of UHF RFID reader has made single-chip UHF RFID reader SoC a hot research topic.Based on the ISO/IEC 18000—6C protocol, this paper proposes a novel system architecture for a UHF RFID reader SoC, analyzes and designs necessary modules such as digital transceiver and protocol processor, and finally releases the digital system which is an essential part of the whole SoC.Multiple modules are integrated into a single chip reader SoC which has different functions such as data communication, protocol processing, and signal processing and so on. Integrating embedded MCU and protocol processor, the proposed system architecture of the reader SoC eases the demand of high performance MCU and reduces hardware cost.Focusing on reader performance, this paper presents a new scheme of digital receiver. Backscattered signals of passive RFID tags which have various energy levels and large frequency variation are handled by AGC and timing synchronizer. A new synchronization scheme employing timing recovery loop is presented to solve the synchronization problem. The receiver is simulated in Matlab and implemented on FPGA platform. Compared with conventional RFID receiver, the proposed scheme is more cost efficient.The digital system including a digital receiver, a digital transmitter, a protocol processor and an embedded MCU is implemented and verified on Xilinx Spartan3A platform. The whole reader chip including a digital system, an RF/analog frontend and ADC/DACs has been realized in SMIC 0.13μm technology. The layout of digital system has an area of 2.5mm*1.2mm including memory. After-layout simulation results prove the function of the digital system.