Research On An Enhancement Mode GaN HEMT Gate Driver Chip

GaN as a third-generation semiconductor has developed rapidly in recent years,because it can achieve higher switching frequency and more efficient power supply and has been gradually applied in various fields.Compared with Si-based devices,enhancement mode GaN devices have lower on-resistance and faster switching frequency,which puts forward higher requirements for their gate drive performance.Therefore,it is of great significance to study the gate drive chips of enhancement mode GaN power devices.Enhancement-mode GaN power devices are often used in high-frequency applications due to their high saturation velocity characteristics.However,when designing GaN-based high-frequency drive circuits,three major problems need to be addressed.1)When designing the gate driver chip of the enhancement mode GaN power device with the half-bridge structure,the CMTI capability is unsatisfied,due to a large dv/dt generated during the fast switching process;2)the propagation delay is large and the matching is poor;3)During the switching process,problems such as negative pressure will be generated at the junction.In this thesis,a driver chip for enhancement mode GaN power devices is designed to detect and limit the input signal,and remove the influence of factors such as burrs from outside the chip.Multiple power rails are designed to drive the normal operation inside the chip.For the dv/dt problem,when designing the level shift circuit,this thesis proposes a method of bypassing the positive and negative feedback circuits to further improve the common mode transient immunity(CMTI)capability;for the transmission delay and matching problems,Use the input detection circuit to limit the input signal to1.8 V,so that a level shift circuit similar to the high-side signal transmission channel can also be designed in the low-side signal transmission channel,try to use low-voltage devices in the chip to reduce the RC delay,and design a high-speed level shift circuit controlled by short pulses to reduce the transmission delay and reduce power consumption.In view of the problem of negative voltage,in the high-side channel,this thesis voltage to use a negative pressure detection circuit on the basis of avoiding the dead time charging is proposed,to double ensure that the node is free from negative pressure,and the charging PMOS transistor is replaced to a NMOS transistor to improve charging.current and avoid insufficient charging;when the low-side negative voltage occurs,this thesis proposes to use a positive and negative power generation circuit to generate-3 V voltage to turn off the low-side enhancement mode GaN power device,and generate a high-side bootstrap circuit at the same time.Turn on the voltage of the charging tube.The chip designed in this thesis is equipped with a protection circuit to improve the reliability of the driver chip.Based on the 0.18 ?m 40 V BCD process,the designed driver chip circuit is designed in this thesis,and the layout planning and post-simulation verification are conducted.The transmission delay of the driver chip designed in this thesis is about 10 ns,and the transmission delay of the high and low channels is less than 4 ns.The CMTI capability of the driver chip exceeds 30 V/ns,the peak value of the input driving signal is 14 V,and the switching frequency reaches more than 1 MHz.The power rail is established stably,and the output signal of the driver chip is stable.