The Optimized Frontend Compiling System Design For Remus Ⅱ Reconfigurable Processor

Coarse-grained reconfigurable processors are increasingly popular bytheir optimized architecture and outstanding performance, which make itpossible for applications to run with high parallel efficiency. But the lack ofadvanced compiling techniques badly influences the programmingefficiency and the processor performace.In this article we introduce a loop-optimized frontend compilingsystem for REmus II coarse-grained reconfigurable processor. Byimproving the compiling flow, simplifying DFG, revising map interfacefile and designing optimizing modules, we solve the configurationstreaming and transferring problem, which makes it possible to improvethe processor’s performance as well as decreasing the compiling time andthe reconfiguring amount.We also introduce for the first time a template-based compilingsystem for REmus II. Starting from compute-bound code parts, we create atemplate-lib system for typical multimedia decoder algorithms, whichinvolve the template structure and developing flow design. Then wecomplete the compiling system with an annotation technique onprogramming codes.A black-box and a white-box testing method are also proposed in thisarticle to test the new compiler’s functionality. Based on these methods andtechniques, our results show that the compiling system has a reasonablebehavior and correct outputs. They also show that the compiling systemeffectively increases the compiled codes’ operating efficiency by about2/3.