H.264Decoder SOC Architecture Based On Co-Processor

H.264/AVC video coding standard can provide much highercompression efficiency than preceding coding standards. However, it hasmuch more hardware complexity for both encoder and decoder, whichbrings some new challenges for system designers. Among all the H.264decoder implementation methods, SOC architeture has been widly usedfor its programbility and flexibility.In this paper a brief introduction of H.264video coding standard anddecoder implementation methods are firstly given. Then based on theanalysis of SOC system acceleration, we present an H.264decoder SOCarchitecture based on co-processor, and proposed the hardwareimplementation of the co-processor.This paper presents a H.264decoder SOC architecture based onco-processor. The co-processor is connected to CPU with a dedicatedinterface, and integrated to the system using ISA extension. In this way,the control logic of co-processor can be very simple, and the software andhardware design of the system can be parallelly developed, which can speed up the system developing process. The proposed co-processorarchiteture and design/verification methods can be easily planted to otherembedded CPU system.In the co-processer design, we analysis the key processes of H.264decoding including intra prediction, inter prediction, IQIT and deblockingfilter. Dedicated hardware acceleration units and correspondingco-processor instructions are designed for each process. The hardwarearchitectures are optimized for low cost and power. The verification resultshows that the co-processor can significantly speed up H.264decodingprocess, and save about76.1%of software decoding time. The systemcan achieve QVGA real-time decoding.